The present invention relates to a semiconductor memory device having open-bit-lines, and particularly to the semiconductor memory device wherein a sufficient operational margin can be retained even when the logic of a bit sequence to be written is shifted to one side.
As a large capacity semiconductor memory device to be used for storing serial data, such as file data, for example, there is known a DRAM (Dynamic Random-Access-Memory) having open-bit-lines.
A prior art of a DRAM of this type is disclosed in a Japanese patent application laid open as a Provisional Publication No. 82086/'97.
FIG. 8 is a block diagram schematically illustrating a configuration of the DRAM according to the prior art.
In the DRAM of FIG. 8, charge of a memory cell 8 selected by a word-line is transferred through a bit-line to a sub-sense-amplifier (hereinafter abbreviated as the SSA) 7, which is shared by four pairs of bit-lines to be connected to the SSA 7 in turn, and amplified to be sensed by a main sense-amplifier (hereinafter abbreviated as the MSA) 6 connected to the SSA 7 with a pair of main bit-lines. The sensed logic of the MSA 6 is latched by a data-latch (hereinafter abbreviated as the DAL) 5.
Thus, data written in a memory cell connected to one of the four pairs of bit-lines of each SSA is latched by each of a number (16, for example) of DALs ranged in columns, selected by a word-line.
The data latched in the DALs are selected in turn by each multiplexer (hereinafter abbreviated as the MUX) 4 controlled by a selection signal YSW and supplied serially to a read-amplifier (hereinafter abbreviated as the RAMP) 3 to be output through a read/write bus (hereinafter abbreviated as the RW bus) 2 and an in/out buffer 100. While the data latched in the DALs are read out serially, data written in memory cells each connected to a next of the four pairs of bit-lines of each SSA are sensed by MSAs to be latched next by the DALs.
By repeating these processes four times by changing the pair of bit-lines to be connected to each SSA, data written in the 64 memory cells, for example, selected by a word-line are read out divided into four sub-cycles, 16 bits per sub-cycle.
When serial data are written in the DRAM, the serial data supplied to the in/out buffer 100 is amplified by a write-amplifier (hereinafter abbreviated as the WAMP) 2 and latched by each of the DALs serially in turn selected by each MUX controlled by the selection signal YSW. After the logic of each bit of the serial data is latched by each of the DALs, it is transferred to each of the MSAs in parallel. The MSA 6 charges a memory cell connected to one of the four pairs of bit-lines through the SSA 7 and selected by a word-line.
By repeating the above processes four times by changing the pair of bit-lines to be connected to each SSA, serial data of 64 bits, for example, are written in 64 memory cells selected by a word-line, 16 bits at a, divided into four sub-cycles.
The open-bit-line DRAM, wherein memory cells are provided for every cross point of the bit-lines and the word-lines, is advantageous for configuring a large scale memory device. However, a demerit of the open-bit-line DRAM is that charges of memory cells easily leak because of noise impressed to word-lines through parasitic capacitances between word-lines and bit-lines, when the logic of a bit sequence to be written is shifted to one side, to `0` or `1`, resulting in decrease of the operational margin necessary for refreshing the memory cells, for example.
For example, in DRAM where each pair of open-bit-lines is used complementarily, potential of either side of the open-bit-lines becomes all HIGH when logic of all bits to be written is either `0` or `1`. Therefore, the potential of inactivated word-lines of the side may be raised near threshold voltage of memory cell MOS transistors through parasitic capacitances such as CP0, CP1, . . . illustrated in FIG. 7, causing leakage of charges of the bit-lines to memory cell capacitors through the memory cell MOS transistors.
When writing or refreshing of the memory cells selected by a word-line is performed divided in four sub-cycles, in such a way as performed in the prior art above described, the noise impressed to the word-lines can be reduced into 1/4, the number of activated bitlines being 1/4. However, there are cases where a 1/4 noise reduction may not be sufficient for retaining a necessary operational margin in DRAMs of large memory capacity. By dividing the writing operation into further sub-cycles, the noise to the word lines may be more reduced. However, the number of access times increases according to number of sub-cycles, resulting in an increase of total cycle time required for writing or refreshing a certain number of memory cells.